module wb_ack_gen(
  input i_wb_clk,
  input i_wb_rst,
  input i_wb_cyc,
  input i_wb_stb,
  output o_wb_ack
);

reg ack;

assign o_wb_ack = ack;

always @(posedge i_wb_clk) begin
  if (i_wb_rst) begin
    ack <= 1'b0;
  end else begin
    ack <= i_wb_cyc & i_wb_stb & ~ack;
  end
end

endmodule
